The invention generally relates to computer systems, and more particularly relates to processor bus interface.
With the advances of semiconductor and computer technology, computer systems are becoming faster and at the same time smaller in size. Desk-top and even lap-top computer systems now possess processing speeds of main-frame computers that used to fill up a small room. Even hand-held computer systems such as personal digital assistants (PDA), which are becoming more popular, are getting more powerful. As computer systems become more miniaturized and inexpensive, more demands are constantly being required of them as well. One such demand is speed or performance.
As computer systems become more powerful and more miniaturized, power-conservation increasingly presents a difficult challenge to overcome. Because of their small size, hand-held computer systems are powered by batteries which have limited operating duration. Since more power is required for faster and more powerful processors, innovative solutions are required to conserve power and thereby extend the battery operating duration.
Within each computer system are many integrated circuits designed to perform different functions such as a memory controller, a hard disk controller, a graphics/video controller, a communications controller, and other peripheral controllers. As is well-known, each of these integrated circuits requires a clock signal to be used as a timing reference in synchronizing the operation of the integrated circuit. In general, power consumption increases as a result of the integrated. circuit being clocked faster.
Periodically, an integrated circuit is not needed and is idle insofar as system functionality is concerned. At other times, while a sub-circuit (e.g., combination logic and data path) that performs data processing and transferring in the integrated circuit is still running, other sub-circuits in the integrated circuit are idle. Because these sub-circuits continue to receive a clock signal, their respective internal sub-circuits continue to be exercised and consume significant power, even while they remain idle. Accordingly, to conserve power, the clock signal to idle sub-circuits is disabled. The clock signal to these sub-circuits is then enabled as necessary. Powering up (enabling) and powering down (disabling) selected sub-circuits in an integrated sub-circuit may occur in a required sequence. Such power sequencing is required because some sub-circuits are dependent on other sub-circuits. For example, a sub-circuit needs to be powered up before another sub-circuit can be powered up. Power sequencing is also required when a sub-circuit needs a sequence of input signals to turn on or off as in the case of some synchronous dynamic Random Access Memory (RAM) or a Liquid Crystal Display (LCD) flat panel monitor. Such power sequence is important because if the sequence is not done properly then some circuitry blocks will not be enabled properly. Power Management Units (PMUs) are used to provide the desired power sequencing related to a power state.
Typically, a PMU supports different power states including but is not limited to a normal power state and low power state. In the normal power state, all sub-circuits in the integrated circuit (e.g., graphics/display controller) may be enabled. Conversely, in the low power state, all sub-circuits in the integrated circuit may be disabled except for the memory buffer refresh logic for refreshing the stored data. Such a low power state is used to conserve power which is crucial in lap-top and hand-held computer systems. However, it is a challenge to power up the integrated circuit in its transition from the low power state to the normal power state because the clock circuit, which is used to generate the internal clock signals for the integrated circuit, has been turned off. A clock signal is required to power up the clock circuit. However, any internal clock that may be available in the integrated circuit during the low power state is not suitable for use in powering up the clock circuit. If the integrated circuit is coupled to a synchronous bus, an external clock signal from the synchronous bus may be available for powering up the clock circuit. On the other hand, if the integrated circuit is coupled to an asynchronous bus, no such external clock is available for powering up the clock circuit if the Phase Lock Loops (PLLs) are turned off. If the PLLs are left enabled during a low power state, they consume a lot of power which is undesirable.
Thus, a need exists for an apparatus, system, and method for powering up the integrated circuit in its transition out of the low power state when the clock circuit supplying the clock signals is turned off.
Accordingly, the present invention provides an apparatus, system, and method for powering up the integrated circuit in its transition out of the low power state when the clock circuit supplying the clock signals is turned off.
The present invention meets the above need with an integrated circuit that is coupled to a central processor. The integrated circuit comprises a processor interface, a power management circuit coupled to the processor interface circuit, and a clock generating circuit coupled to the processor interface circuit and the power management circuit.
The processor interface circuit provides an interface between the integrated circuit and the central processor. The processor interface circuit comprises a set of registers for storing programmed information from the central processor wherein the programmed information includes information on a desired power state of the integrated circuit and enabling data bits. This is the set of registers accessible during a first (low) power state. The power management circuit controls the desired power state of the integrated circuit in response to programmed information stored in the set of registers. The power management circuit supports at least the first (low) power state and a second (normal) power state. The power management circuit performs power sequencing to transition between two power states. The clock generating circuit is controlled by the power management circuit and the programmed information stored in the set of registers such that during the first power state, the clock generating circuit is substantially disabled for power conservation and during the second power state, the clock generating circuit is enabled for operating the integrated circuit.
In an alternate embodiment, the clock generating circuit may further comprise an oscillator circuit and a plurality of Phase Lock Loop (PLL) circuits coupled to the oscillator circuit. The oscillator circuit generates a reference clock signal. The plurality of PLL circuits generate derivation clock signals based on the reference clock signal. The programmed information further comprises multiplication and division factors used by the PLL circuits in generating the derivation clock signals.
All the features and advantages of the present invention will become apparent from the following detailed description of its preferred embodiment whose description should be taken in conjunction with the accompanying drawings.